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Semiconductor Bumps
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Wafer bumping requires dedicated new inspection methods to ensure profitable yields as device I/O counts increase and bump pitches tighten. The qualification of bumped die and the maintenance of bumping processes also require optical inspection of every bump on every die on each wafer. Bumps that are outside the specified levels will not adhere well to the package, indicating potential issues in electroplating. 3D bump inspection by PhaseView can measure bumps height, co-planarity, roughness and morphology, providing high throughput (1 sec per 1M pixel measurement), nanometer accuracy and high repeatability. PhaseView's optical instruments can classify wafer surfaces according to their roughness, and measure bump heights. As an example, SurPhase HS can measure bumps heights around 150-170 μm and consistently yield numbers +/- 0.1μm measuring several bumps per image. |
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